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Book Details
A System Verilog Primer
Author(s) :J. Bhaskar

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ISBN : 9788178002804
Name : A System Verilog Primer
Price : Currency 795.00
Author/s : J. Bhaskar
Type : Text Book
Pages : 350
Year of Publication : Rpt. 2024
Publisher : BS publications / BSP Books
Binding : Paperback
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Contents

1. Introduction, 2. Language Elements, 3. Composite Types, 4. Expressions, 5. Behavioral Modeling, 6. Structural Modeling, 7. Other Topics, 8. Advanced Verification Topics, 9. Assertions

About the Author

J. Bhasker is an Architect at eSilicon Corporation. Prior to that, he was a Distinguished Member of Technical Staff at Bell Laboratories. He has received a Meritorious Service Award from IEEE Computer Society for his technical contributions and continued leadership in the development of the EDA standards, especially the VHDL and Verilog RTL synthesis standards.
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