About the Book:
"Verilog® HDL Synthesis: A Practical Primer." This comprehensive guide unravels the complexities of Verilog language, offering a detailed exploration of its features and applications in hardware modeling. Through numerous examples and clear explanations, readers will grasp how to effectively utilize language constructs to simulate and verify hardware designs. From different modeling styles to stimulus and control descriptions, this book equips you with the knowledge to master Verilog with ease. Whether you're a novice seeking to understand the basics or a seasoned professional looking to enhance your skills, this primer presents Verilog syntax in a reader-friendly format, making it an invaluable resource for anyone delving into digital design.
Contents
1. Basics, 2. Verilog Constructs to Gates, 3. Modeling Examples, 4. Model Optimizations, 5. Verification
About the Author
J. Bhasker is the chair of the IEEE PAR 1364.1 verilog synthesis interoperability working Group that is working towards standardizing a Verilog subset for RTL synthesis. He is one of the main architects of the ArchSyn Synthesis system developed at Bell labs. He has taught Verilog HDL and Verilog HDL Synthesis to many AT & T / Lucent designers. He is also the author of the best selling book" A Verilog HDL Primer"
