Contents

1. Basics, 2. Verilog Constructs to Gates, 3. Modeling Examples, 4. Model Optimizations, 5. Verification 

About the Author

J. Bhasker is the chair of the IEEE PAR 1364.1 verilog synthesis interoperability working Group that is working towards standardizing a Verilog subset for RTL synthesis. He is one of the main architects of the ArchSyn Synthesis system developed at Bell labs. He has taught Verilog HDL and Verilog HDL Synthesis to many AT & T / Lucent designers. He is also the author of the best selling book" A Verilog HDL Primer"